The present invention relates to digital tests and, in particular, to apparatus that monitors a plurality of lines to provide therefrom a single error signal.
It is known to employ a parity generator to supplement a transmitted or stored digital signal. This parity generator produces an addition data bit which renders the number of high signals (digital ones) in the group either even or, for some embodiments, odd. Thus, when transmitted data is received or removed from memory its validity can be ascertained by determining that the parity of the signal is correct. This technique is particularly effective where one of the data lines has failed and is producing a constant erroneous signal.
It is important during manufacture, in the field and at other times to test digital equipment for faults. Complete testing of digital systems is difficult because of the extremely large number of valid states which the system can assume and the great number of signal lines which may be monitored. Often, it is not practical to sequence a piece of digital equipment through all of its possible states and monitor each data line during each state because of the vast number involved and because of time limitations.
A conventional technique for testing digital equipment is routing a limited number of test points from the circuit to a connector, such as an edge connector for a printed circuit board. Of course, the number of test points must be limited since a printed circuit board can accommodate only a limited number of interconnecting runs and contact pads for edge connectors.
For this reason, known error checking circuits employ AND or OR gates for monitoring the validity of the outputs from a one out of N decoder. A one out of N decoder typically responds to binary coded data by producing a singular or strobed signal on one of N lines. The inputs of such an AND or OR gate are connected to these N lines to produce an error signal if all of the monitored lines are improperly, in the same state. This latter technique however, fails to detect a common failure mode wherein the strobing of one particular line erroneously causes simultaneous strobing of another line.
Parity checkers have been proposed in the literature for monitoring a plurality of internal points on a printed circuit board and transmitting a single error signal. This approach has been proposed for monitoring the flip flops, the carry outputs of counters and the final outputs of shift registers.
None of the above approaches have considered the significant testing problems inherent in monitoring the strobed output lines from a one out of N decoder. Therefore, there is a need for circuitry and a method for testing strobed lines to detect a failure such as strobing on two lines. The approach ought not to require excessive wiring or an excessively large connector.